A SMP architecture is a system with centralized shared memory operating under a single operating system (OS). A device such as a computing device or network device that has an SMP architecture has a set of homogenous processors or “cores” executing processes independent of one another. The cores can be components on the same physical die or similarly tightly coupled processing elements. This tightly coupled set of processing elements, either processors or cores, can be referred to as a central processing unit (CPU). The processors or cores, referred to herein simply as cores, for sake of convenience and clarity, share a main memory and each have separate caches.
In the SMP based architecture, a scheduler of the OS decides which core a process will run on. Each process is assigned an affinity mask by the OS, which is a set of bits that each correspond to one of the available cores indicating whether the respective core is preferred for process assignment for the corresponding process. By default, the process's affinity mask is set to all 1 s, meaning that the scheduler is allowed to dispatch this process to any core without any preference, instead determining the assignment based on whichever core is idle. The affinity mask associated to a process can be changed to include or exclude certain cores and if so configured then the scheduler will dispatch the process only to those cores that are set in the affinity mask. The scheduler will assign each process a core and give it a set of time or cycles for execution, referred to as a time slice. However, once the affinity mask is set, the OS will not change it automatically to better utilize unused processors or cores even if a process has to wait to be executed by the assigned core while other cores are available.
When there is heavy demand for the resources of the CPU (i.e., the main memory and cores) by multiple processes at the same time and each process needs an assigned core of the CPU for much longer than its time slice then OS performance is hit by continuous cache clean up that occurs in each core because under SMP architecture the processes get dispatched randomly to any core whichever is available. The OS performance is hit the worst if an interrupt storm (a large number of clustered interrupts) also occurs during the high CPU usage interval because some interrupts are handled by the OS on designated cores only and this increases the likelihood that a process's data in the cache of the assigned core will be cleared before it gets rescheduled on the same core next time.
On the other hand if a process's affinity is set permanently to a fixed core then the process loses the advantage of operating in a multi-processor or multi-core system (i.e., an SMP architecture), because if the assigned cores are busy when the process needs CPU resources, then the process will have to wait for them to become free even though the other cores in the system were available.